About Me
I am a PhD researcher at Aalto University (Finland), advised by Professor Martin Andraud. I received my M.Sc. in Micro- and Nanoelectronic Circuit Design from Aalto in 2022, where I explored number systems for probabilistic circuits and their application to self-adaptive RF transceivers. My research focuses on energy-efficient hardware and algorithms for probabilistic, tractable, and neuro-symbolic AI, ranging from CUDA kernels for log-domain inference (6–10× speedup) to a taped-out 16 nm accelerator, with an emphasis on approximate computing and hardware/software co-design.
I have also been a visiting scholar at MICAS, KU Leuven (Belgium) under Professor Marian Verhelst, where I led the backend and silicon testing of our neuro-symbolic AI chip.
News
- Apr 2026Presented EinChip, our neuro-symbolic AI accelerator, at IEEE CICC 2026.
- Mar 2026Attended the Dagstuhl Seminar Tensor Factorizations Meet Probabilistic Circuits.
- Aug 2025Our LogSumExp accelerator paper was accepted in IEEE TCAS-I.
- Aug 2025Back at KU Leuven for silicon testing and performance characterization of our chip.
- Jul 2025Co-organized the 8th Workshop on Tractable Probabilistic Modeling (TPM 2025) at UAI 2025.
- Oct 2024Visiting KU Leuven to finalize the backend of our AI chip for tape-out.
- Jun 2024Presented at the Nordic Probabilistic AI Summer School in Copenhagen.
- Apr 2024Our paper on hardware-efficient inference in probabilistic circuits was accepted at UAI 2024.
Publications
- CICC '26 L. Yao, S. Zhao, M. Verhelst, M. Andraud. EinChip: A 4.6/1.5 TOPS/W 6/24b Log-compute Einsum-based Accelerator for Neuro-Symbolic AI.
- TCAS-I '25 L. Yao, S. Zhao, M. Trapp, J. Leslin, M. Verhelst, M. Andraud. LogSumExp: Efficient Approximate Logarithm Acceleration for Embedded Tractable Probabilistic Reasoning. [PDF]
- UAI '24 L. Yao, M. Trapp, J. Leslin, G. Singh, P. Zhang, K. Periasamy, M. Andraud. On Hardware-Efficient Inference in Probabilistic Circuits. [PDF]
- NEWCAS '24 K. Periasamy, J. Leslin, A. Korsman, L. Yao, M. Andraud. AutoPC: An Open-Source Framework for Efficient Probabilistic Reasoning on FPGA Hardware. [PDF]
- TPM '23 L. Yao, M. Trapp, K. Periasamy, J. Leslin, G. Singh, M. Andraud. Logarithm-Approximate Floating-Point Multiplier for Hardware-Efficient Inference in Probabilistic Circuits. [PDF]
- PGM '22 J. Leslin, A. Hyttinen, K. Periasamy, L. Yao, M. Trapp, M. Andraud. A Hardware Perspective to Evaluating Probabilistic Circuits. [PDF]
Education
Awards & Grants
- HPY Research Foundation Grant: AI-based self-adaptive RF transceiver using hardware-efficient probabilistic models
- Aalto University: Full Admission Scholarship (M.Sc.), Dean Scholarship, Incentive Scholarship
- Central South University: Academic Prizes (2016–2019) and National Encouragement Scholarship of China
Curriculum Vitae
Contact
Email: lingyun.yao@aalto.fi