About Me
I am a PhD researcher at Aalto University (Finland), advised by Professor Martin Andraud. I work at the meeting point of machine learning and hardware design, motivated by one question that I find endlessly interesting: how can we make AI far more efficient without giving up what makes it powerful? As models keep growing and energy budgets keep shrinking, I am convinced that the biggest gains come from designing algorithms and the silicon they run on together, rather than treating them as separate problems.
I received my M.Sc. in Micro- and Nanoelectronic Circuit Design from Aalto in 2022, where I explored number systems for probabilistic circuits and their use in self-adaptive RF transceivers. Since then my work has come to span the full stack of efficient AI. On the algorithm side, I design approximate-computing methods that make probabilistic AI inference faster and more energy efficient, including GPU kernels for general-purpose hardware. On the hardware side, I bring these ideas to custom circuits on FPGA and all the way to silicon, designing approximate-computing units and taping out our neuro-symbolic AI accelerator, EinChip. As a visiting scholar at MICAS, KU Leuven (Belgium) under Professor Marian Verhelst, I worked on the backend and silicon testing of EinChip.
I enjoy moving between these two worlds and translating between the machine-learning and hardware-design communities. Increasingly, my curiosity pulls me toward the theory behind efficiency, guided by a belief that there is almost always a cheaper way to solve a problem once we understand it deeply enough. I want to find those solutions and make energy-efficient AI practical far beyond the data center, on the resource-constrained devices where efficiency matters most.
News
- Apr 2026Presented EinChip, our neuro-symbolic AI accelerator, at IEEE CICC 2026.
- Mar 2026Attended the Dagstuhl Seminar Tensor Factorizations Meet Probabilistic Circuits.
- Aug 2025Our LogSumExp accelerator paper was accepted in IEEE TCAS-I.
- Aug 2025Back at KU Leuven for silicon testing and performance characterization of our chip.
- Jul 2025Co-organized the 8th Workshop on Tractable Probabilistic Modeling (TPM 2025) at UAI 2025.
- Oct 2024Visiting KU Leuven to finalize the backend of our AI chip for tape-out.
- Jun 2024Presented at the Nordic Probabilistic AI Summer School in Copenhagen.
- Apr 2024Our paper on hardware-efficient inference in probabilistic circuits was accepted at UAI 2024.
Publications
- CICC '26 L. Yao, S. Zhao, M. Verhelst, M. Andraud. EinChip: A 4.6/1.5 TOPS/W 6/24b Log-compute Einsum-based Accelerator for Neuro-Symbolic AI.
- TCAS-I '25 L. Yao, S. Zhao, M. Trapp, J. Leslin, M. Verhelst, M. Andraud. LogSumExp: Efficient Approximate Logarithm Acceleration for Embedded Tractable Probabilistic Reasoning. [PDF]
- UAI '24 L. Yao, M. Trapp, J. Leslin, G. Singh, P. Zhang, K. Periasamy, M. Andraud. On Hardware-Efficient Inference in Probabilistic Circuits. [PDF]
- NEWCAS '24 K. Periasamy, J. Leslin, A. Korsman, L. Yao, M. Andraud. AutoPC: An Open-Source Framework for Efficient Probabilistic Reasoning on FPGA Hardware. [PDF]
- TPM '23 L. Yao, M. Trapp, K. Periasamy, J. Leslin, G. Singh, M. Andraud. Logarithm-Approximate Floating-Point Multiplier for Hardware-Efficient Inference in Probabilistic Circuits. [PDF]
- PGM '22 J. Leslin, A. Hyttinen, K. Periasamy, L. Yao, M. Trapp, M. Andraud. A Hardware Perspective to Evaluating Probabilistic Circuits. [PDF]
Education
Awards & Grants
- HPY Research Foundation Grant: AI-based self-adaptive RF transceiver using hardware-efficient probabilistic models
- Aalto University: Full Admission Scholarship (M.Sc.), Dean Scholarship, Incentive Scholarship
- Central South University: Academic Prizes (2016–2019) and National Encouragement Scholarship of China
Curriculum Vitae
Contact
Email: lingyun.yao@aalto.fi